Ventana tempts hyperscalers with customized RISC-V server chip • The Register

RISC-V Summit Ventana Micro Methods is about to unveil a household of datacenter-class processors primarily based on the RISC-V structure, which it claims will enable patrons to customise the chips to fulfill their necessities by combining Ventana’s CPU cores with different silicon.

To be formally introduced at this week’s RISC-V Summit in San Jose, Ventana’s Veyron V1 is being hailed by the corporate as the primary RISC-V chip to be aggressive towards present datacenter processors by way of single thread efficiency.

The corporate got here out of stealth mode final yr.

“Our most important aim was to create a world class, excessive efficiency RISC-V processor that’s going to be aggressive relative to all the things else that’s on the market available in the market at present,” Ventana founder and CEO Balaji Baktha informed us.

Excessive single thread efficiency is a key requirement for Ventana’s goal market: hyperscalers. One other function meant to please them is the processor structure, which lets clients to assemble their very own system-on-chip (SoC) design from chiplets, permitting them so as to add customized silicon to a number of chiplets with Veyron V1 cores.

This method apparently owes a lot to Cisco, which was an early investor in Ventana, based on Baktha.

“We realized chiplets had been one of the simplest ways to productize this to permit hyperscalers to customise the top SoC to suit their specific workload wants,” he stated. “That was the founding premise, and we had been in a position to work with varied enterprise models inside Cisco to assemble up all the {hardware} necessities, all the software program necessities, and proactively meld them collectively to provide you with an answer that they might see as acceptable.”

AWS and Google know easy methods to construct an SoC as a result of they’ve already carried out it, Baktha identified, citing examples such because the AWS Graviton processors.

“However constructing CPU cores, that’s one other story, they don’t have these form of groups in-house,” he claimed, “So when you can ship the compute portion of it within the type of a chiplet as a identified good die, that removes the hurdle of them having to do this in-house.”

What Ventana is providing the hyperscalers is a equipment from which they’ll assemble their very own SoCs to their very own necessities. This includes a number of Veyron compute chiplets, a reference I/O hub chip design, and the die-to-die interconnect know-how to tie all of it collectively.

“All they must do is take the I/O hub, and customise it. Customizing that I/O hub is so simple as dropping in an accelerator or no matter you might have seen engaged on an FPGA, and hastily they’ve a custom-made SoC,” Baktha stated, claiming that this method would save hyperscale clients at the least $75 million and a minimal of two years of design improvement cycle time to create a customized SoC.

One other benefit, based on Baktha, is that Ventana’s die-to-die interconnect is parallel, slicing out undesirable latency.

“Till now, all people has carried out a serialised interconnect, largely a SerDes-based die-to-die interconnect. Now we have a parallel die-to-die interconnect. Why is that essential? Serial interconnects take about 120 to 130 nanoseconds to speak between them. With parallel, that latency is seven nanoseconds, which is similar to a single die monolithic design,” he claimed.

In truth, Ventana is pursuing three routes to market; the primary is to produce each the compute chiplets and I/O hub, the second is to let the shopper construct their very own customized I/O hub, maybe supporting HBM reminiscence for top efficiency computing, for instance, and the third is IP licensing, in case a buyer needs a smaller variety of compute cores, for instance.

That Ventana compute chiplet includes 16 RISC-V cores with 48MB of shared L3 cache, clocked at 3.6GHz. Initially, the chiplets will likely be manufactured by TSMC utilizing a 5nm manufacturing node, whereas the I/O hub or different elements will be manufactured utilizing much less leading edge nodes, maybe 12nm or 16nm.

Clients can mix the compute chiplets to construct an SoC with as much as 192 cores, based on Ventana.

The corporate additionally claims to have plenty of chiplet companions it has assembled that may present chiplets with different features or implement an SoC for purchasers. The record contains Apex Semiconductor, Silicon Field, FLC Expertise Group and Bolt Graphics.

In the meantime, the fantastic thing about the RISC-V ecosystem is that there’s already software program assist from the open supply neighborhood, together with Linux distributions akin to Ubuntu and Debian, together with functions akin to Ceph storage, NGINX, MySQL, OpenJDK and Redis.

One other declare is that as a result of it’s a clear slate design, Ventana has been in a position to keep away from the form of flaws which have led to side-channel assaults of the type seen within the Spectre or Meltdown exploits in different processors. We suspect this sort of declare may be tempting destiny.

Andrew Buss, IDC Senior Analysis Director for Europe, informed us that this launch is coming at an attention-grabbing time due to the emergence of Arm-based options into the general public cloud platforms, representing a divergence from the normal x86 dominance.

“The software program ecosystem is maturing and we’re shifting to a state of affairs the place appropriate code and likewise multi-platform moveable code is making this possible,” he stated.

For RISC-V, it might appear like it’s late to the get together, and the momentum is now with Arm. Nevertheless, “the identical developments enabling Arm may also work for RISC-V and so they should be investing in getting the identical ecosystem assist to make it viable,” Buss added.

However Arm has probably not helped its case with the Qualcomm lawsuit, based on Buss, exhibiting that in lots of instances, Arm is sort of restrictive in what it can license and this may restrict customization choices.

Manoj Sukumaran, Omdia Principal Analyst for DataCenter Compute & Networking, stated there may be rising curiosity in various CPU architectures as a result of geopolitical and commerce tensions are inflicting know-how insecurity in a number of nations.

He informed us that he thought it possible that the Ventana chip would function an R&D platform for the RISC-V software program stack, and should not see a lot main buyer adoption.

“The software program ecosystem for RISC-V remains to be very nascent and that would be the greatest barrier for adoption. However it’s positively an incredible begin, having a platform designed for server workloads creates quite a lot of momentum for software program improvement efforts,” he stated.

With the Veyron V1 now formally launched, Ventana stated it expects that early clients could have first manufacturing silicon by Q2 or Q3 2023.

The corporate is already engaged on a second technology product, which it expects to ship a big instruction per clock (IPC) efficiency increase in comparison with this design and might even see the sunshine of day as quickly as 2024.

“In a method, we’ve parallelized the event course of to permit us to form of drive v2 design in a short time, with samples coming a couple of yr after the samples for v1,” Baktha stated. ®